1. Field of the Invention
The present invention generally relates to semiconductor devices and a method of fabricating the same and, more particularly, to a phase changeable memory cell array region and methods of forming the same.
A claim of priority is made to Korean Patent Application No. 10-2005-0108797, filed Nov. 14, 2005, the entirety of which is incorporated by reference.
2. Description of Related Art
Nonvolatile memory devices do not lose stored data even in the event of an abrupt loss of power supply. For at least this reason, nonvolatile memory devices are widely used in computers, mobile telecommunication systems, memory cards, and other such applications.
Various types of nonvolatile memory devices may be used in electronic equipment. For example, a flash memory device is a widely used type of a nonvolatile memory device. A flash memory device is configured to store memory even in the event of an abrupt loss of power. Typically, the flash memory device includes memory cells with stacked gate structures. The stacked gate structures include a number of components. In particular, the stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode, which are sequentially stacked on a channel region. In addition, the stacked gate structure may include other components that may be used to store data.
Various techniques may be used to improve the working of the flash memory device. For example, in order to improve the reliability and programming efficiency of the memory cells of the flash memory device, the film quality of the tunnel oxide layer may be improved and the coupling ratio of the memory cells may be increased.
While flash memory devices are extensively used in various applications, efforts have been made to introduce new nonvolatile memory devices in the market. One such nonvolatile memory device is a phase changeable memory device. A phase changeable memory device includes a number of components. For example, a unit cell of the phase changeable memory device includes a switching device. The unit cell also includes a data storage element that is connected in series to the switching device. The data storage element includes a lower electrode electrically connected to the switching device, a phase changeable material pattern disposed on the lower electrode, and an upper electrode disposed on the phase changeable material pattern. In general, the lower electrode functions as a heater. Specifically, when a write current flows through the switching device and the lower electrode, heat is generated at an interfacial surface between the phase changeable material pattern and the lower electrode. The generated heat changes the phase changeable material pattern into an amorphous or crystalline state.
Conventionally, a phase changeable material layer of the phase changeable memory device is shaped as an island which is separately disposed in each memory cell. The phase changeable material layer may be shaped as an island using a number of processes. For example, an etching process may be performed to form the phase changeable material layer in the island shape.
The use of an etching process may cause undesirable changes in the phase changeable material. For example, the properties of a separated surface of the phase changeable material layer may change due to the etching process. Furthermore, the separated surface of the phase changeable material layer may come into contact with, for example, an interlayer dielectric layer. This contact between the phase changeable material and the interlayer dielectric layer may change the composition of the phase changeable material. Because of the undesirable changes in the phase changeable material, the amount of normal phase changeable region available for programming is reduced. This reduction in the amount of phase changeable region available for programming may affect the functionality of the phase changeable memory cell.
Furthermore, even if a phase changeable memory device is programmed initially, a portion exposed by the separated surface of the phase changeable material layer may deteriorate over a period of time. This deterioration may reduce the number of times that the phase changeable memory device can be re-written to.
Numerous efforts have been directed towards preventing the above-mentioned problems from surfacing in phase changeable memory devices. For example, Korean Laid-open Publication No. 10-2004-0100867 for “Semiconductor Integrated Circuit Device” by Takaura, Norikatsu et al. (“Norikatsu”) discloses a method of preventing degradation of the properties of the phase changeable memory cell during the etching process of the phase changeable material layer. According to Norikatsu, when a cell size is reduced to increase the integration density of a semiconductor device, a common memory cell upper plate electrode that is connected to a power line, is formed on a phase changeable material layer in a memory cell region. The memory cell region also includes a resistor device for a phase changeable memory. Furthermore, the phase changeable material layer is shared between the resistor device and the electrode. Thus, the phase changeable material layer is not exposed except for a memory cell positioned at the outermost circumferential portion of a memory cell region.
Because a major portion of the phase changeable material is not exposed, neither the shape of the memory cell nor the composition of the phase changeable material layer is affected by an etching process. Therefore, despite the use of the etching process to shape the phase changeable material layer, the electrical properties of the memory cell formed by the method of Norikatsu may be uniform. The uniform electrical properties of the memory cell may improve the reliability of the memory cell.
While the Norikatsu memory cell may have improved reliability, it has several shortcomings. For example, the phase changeable material layer in the phase changeable memory cell of Norikatsu may cause thermal disturbance between adjacent memory cells. Furthermore, when a distance between the memory cells decreases with an increase in the integration density of semiconductor devices, the thermal disturbance may increase. For example, when a memory cell A is in a low resistive state (i.e., a “0” state) and a memory cell B adjacent to the memory cell A is in a high resistive state (i.e., a “1” state), heat generated at an interfacial surface between a lower electrode of the memory cell B and the phase changeable material layer in memory cell B may melt the phase changeable material layer in memory cell B. In this case, because the phase changeable material layer in the memory cell A is connected to the phase changeable material layer in the adjacent memory cell B, the phase changeable material layer transmits heat from the memory cell B to the memory cell A. This heat transfer from memory cell B to memory cell A may cause the temperature of the memory cell A to increase. The increase in temperature of memory cell A may cause, memory cell A to transition from the low resistive state (i.e., the “0” state) to a higher resistive state. As a result, the memory cell A may lose specific data corresponding to the “0” state and may therefore not function as a memory cell any more.
The present disclosure is directed towards coming one or more problems associated with the prior art phase changeable memory devices.